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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
? The product of CLKIN and PLLM must never exceed 1/2
f VCO (max) in Table 11 if the input divider is not enabled
(INDIV = 0).
? The product of CLKIN and PLLM must never exceed f VCO
(max) in Table 11 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
f VCO = 2 × PLLM × f INPUT
f CCLK = (2 × PLLM × f INPUT ) ÷ (2 × PLLN )
f INPUT = CLKIN ÷ 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 9 . All
of the timing specifications for the ADSP-2136x peripherals are
defined in relation to t PCLK . Refer to the peripheral specific sec-
tion for each peripheral’s timing information.
Table 9. Clock Periods
Timing
where:
f VCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
Requirements
t CK
t CCLK
t PCLK
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t CCLK
using the CLK_CFG pins in hardware.
PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
f INPUT = Input frequency to the PLL.
f INPUT = CLKIN when the input divider is disabled or
PLL
Figure 5 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, refer to the ADSP-2136x SHARC Processor
Hardware Reference .
CLKIN
CLKIN
DIVIDER
f INPUT
LOOP
FILTER
VCO
f VCO
PLL
DIVIDER
f CCLK
CCLK
XTAL
BUF
PMCTL
(INDIV)
CLK_CFGx/
PMCTL (2 × PLLM)
PMCTL
(2 × PLLN)
PMCTL
(PLLBP)
DIVIDE
BY 2
PCLK
f VCO ÷ (2 × PLLM)
PMCTL (CLKOUTEN)
CLKOUT (TEST ONLY)*
RESETOUT
RESET
DELAY OF
4096 CLKIN
RESETOUT
BUF
CYCLES
CORERST
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f INPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
Figure 5. Core Clock and System Clock Relationship to CLKIN
Rev. J |
Page 17 of 60 |
July 2013
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